The data in the TX modulator shift register are always shifted out LSB-first to generate the
serial transmit data stream (see Figure 3-22). If an MSB-first data stream is required, the current byte is flipped
before it is loaded to the shift register. This is done automatically for data from the SFIFO
and the stop sequence, which are always sent MSB-first (see Table 3-41).
Data from the DFIFO including the optional CRC checksum can be transmitted MSB-first or
LSB-first, depending on the setting in TMCR2.TMMSB.
The CRC checksum is given special treatment when loaded to the shift register as depicted in
the following figure. In case of an MSB-first setting, the entire valid checksum is flipped
before it is loaded to the shift register instead of a byte-wise flipping.Figure 3-25. TX Modulator LSB/MSB Processing for
CRC
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