2.8.4.5 Polling Cycle Calibration
The ATA8510/15 offers a calibration procedure to ensure high accuracy of the adjusted polling cycle. The polling cycle is calibrated after the power-on when the SRC bit is preselected in the eepConfValid.confInitFlags EEPROM setting.
| Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
| 0x0008 | confInitFlags | AntTune | TempMeas | SRC | FRC | — | — | — | — |
This procedure can be done periodically as a sub-task of the system self-check and calibration. This applies only if the clock source of Timer1 is set to SRC. The EN_SRCCAL bit in the calConf1 EEPROM setting must be set in order to enable the polling cycle calibration during the system self-check and calibration procedure.
| Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
| 0x001C | calConf1 | — | EN_TEMP_MEAS | EN_SRCCAL | EN_FRCCAL | — | — | — | EN_REGREFRESH |
The polling cycle calibration requires additional time. For more information about the polling cycle calibration, see Tune and Check.