2.8.4.2 Polling Cycle
The polling cycle consists of the active polling period and the sleep period, as illustrated in the following figure. The timing interval to start the next polling cycle is programmable between 0 ms and 4 ms and is controlled by Timer1.
The clock source for the polling timer is defined in an EEPROM variable. To select the clock source for Timer1 as well as to adjust a proper polling cycle, the eepPollLoopConf.confT1MR and eepPollLoopConf.confT1COR EEPROM variables must be modified (see sEEPromPollLoopConf eepPollLoopConf).
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|---|---|
0x0099 | confT1COR | T1COR[7:0] | |||||||
0x009A | confT1MR | T1DC[1:0] | T1PS[3:0] | T1CS[1:0] |
The RX_ACTIVE pin (PB7) can be configured to monitor the status of the RF front end during receive mode. The polarity of the pin can be adjusted in the EEPROM setting as described in sEEPromEventConfig eepEventConf.
The sleep period is primarily intended to keep the current consumption at the lowest possible level. The ATA8510/15 turns the receiver path off during the sleep period for this reason. Only the polling timer together with the selected oscillator remain active. Using the SRC oscillator to clock the polling timer is recommended due to its low power consumption and cyclical calibration of the polling cycle.
End of Polling Cycle (EOP)
A service/channel configuration with an activated EOP label defines the last configuration in the active polling period. When detecting this label, the firmware enters the polling sleep period. Otherwise, the next configuration is triggered.