11.2.21 CAN Receive Overflow Interrupt Status Register Low(1)
Note:
- C1RXOVIFL: FIFO: RFOVIFx (flag needs to be cleared in the FIFO register).
| Name: | C1RXOVIFL |
| Offset: | 0x5E8 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RFOVIF[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RFOVIF[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – RFOVIF[15:8] Unimplemented
Bits 7:0 – RFOVIF[7:0] Receive FIFO Overflow Interrupt Pending bits
| Value | Description |
|---|---|
1 |
Interrupt is pending. |
0 |
Interrupt is not pending. |