17.6.1 Principle of Operation

The OSCCTRL bus clock (CLK_OSCCTRL_APB) is required to access the OSCCTRL registers. This clock must be enabled in the MCLK - Main Clock.

The OSCCTRL gathers controls for XOSC, OSC48M, and FDPLL96M and provides these clock sources to the GCLK - Generic Clock Controller.

Through this interface these oscillators are enabled, disabled, or have their calibration values updated.

The Status register gathers different status signals coming from the oscillators controlled by the OSCCTRL. These status signals can be used to generate system interrupts, and in some cases wake the system from Sleep mode, provided the corresponding interrupt is enabled.