33.7.6 RAM Watchdog
This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and
CCCR.INIT = 1.
The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via
the CAN’s AHB Host Interface starts the Message RAM Watchdog Counter with the value
configured by RWD.WDC. The counter is reloaded with RWD.WDC when the Message RAM signals
successful completion by activating its READY output. In case there is no response from
the Message RAM until the counter has counted down to zero, the counter stops and
interrupt IR.WDI is set.
| Name: | RWD |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Read-only, Write-restricted |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | WDV[7:0] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | WDC[7:0] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – WDV[7:0] Watchdog Value
Actual Message RAM Watchdog Counter Value.
Bits 7:0 – WDC[7:0] Watchdog Configuration
Start value of the Message RAM Watchdog Counter. With the reset value
of 0x00 the counter is disabled.
