5.15.11.3 System Interrupt Register 1
Name: | SIR1 |
Offset: | 0x13 |
Reset: | 0x20 |
Property: | R, R/W |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
VSUPF | WAKE | SYS | ILIM | LDOF | OVTF | VDSSC | VGSUV | ||
Access | R | R | R | R/W | R | R | R | R | |
Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – VSUPF
(Submit Feedback)Value | Description |
---|---|
1 | SIR5[7] and/or SIR5[6] bits are set to ‘1’. |
0 | Both SIR5[7] and SIR5[6] bits are cleared. |
Bit 6 – WAKE
(Submit Feedback)Value | Description |
---|---|
1 | SIR5[5] and/or SIR5[4] bits are set to ‘1’. |
0 | Both SIR5[5] and SIR5[4] are cleared. |
Bit 5 – SYS
(Submit Feedback)Value | Description |
---|---|
1 | SIR5[3] and/or SIR5[2] and/or SIR5[1] bits are set to '1'. |
0 | SIR5[3:1] is cleared. |
Bit 4 – ILIM
(Submit Feedback)Value | Description |
---|---|
1 | A power stage current limitation event has been detected. |
0 | The bit is reset to ‘0’ by writing a ‘1’ to the bit or, when unlatched current limitation handling has been enabled, the ILIM bit will be cleared when any of the six gate control driver outputs are activated. |
Bit 3 – LDOF
(Submit Feedback)Value | Description |
---|---|
1 | Any SIR2 register bits are set to ‘1’. |
0 | All of the SIR2 register bits are reset to ‘0’. |
Bit 2 – OVTF
(Submit Feedback)Value | Description |
---|---|
1 | Any of the SIR4 register bits are set to ‘1’. |
0 | All of the SIR4 register bits are reset to ‘0’. |
Bit 1 – VDSSC
(Submit Feedback)Value | Description |
---|---|
1 | A VDS short circuit failure has been detected by at least one bit in SIR3[5:0] (at least one bit is set to ‘1’). |
0 | All of the bits in SIR3[5:0] are cleared. |
Bit 0 – VGSUV
(Submit Feedback)Value | Description |
---|---|
1 | A VGS undervoltage failure has been detected by at least one bit in SIR3[7:6] (at least one bit is set to ‘1’). |
0 | Both of the bits in SIR3[7:6] are cleared. |