5.15.11.3 System Interrupt Register 1

The SIR1 register shows the overall failure interrupt events. The bits are not latched, except for bit 4 (ILIM). The state of these flags is the result of the OR-ed operation with the latched bits from SIR2, SIR3, SIR4 and SIR5. The SIR1 bits will be automatically cleared after the corresponding SIR2-SIR5 bits are cleared.
Name: SIR1
Offset: 0x13
Reset: 0x20
Property: R, R/W

Bit 76543210 
 VSUPFWAKESYSILIMLDOFOVTFVDSSCVGSUV 
Access RRRR/WRRRR 
Reset 00100000 

Bit 7 – VSUPF

IC Supply Failure Event Interrupt bit
ValueDescription
1 SIR5[7] and/or SIR5[6] bits are set to ‘1’.
0 Both SIR5[7] and SIR5[6] bits are cleared.

Bit 6 – WAKE

Wake-Up Event Interrupt bit
ValueDescription
1 SIR5[5] and/or SIR5[4] bits are set to ‘1’.
0 Both SIR5[5] and SIR5[4] are cleared.

Bit 5 – SYS

System Event Interrupt bit
ValueDescription
1 SIR5[3] and/or SIR5[2] and/or SIR5[1] bits are set to '1'.
0 SIR5[3:1] is cleared.

Bit 4 – ILIM

Power Stage Current Limitation Interrupt bit
ValueDescription
1 A power stage current limitation event has been detected.
0 The bit is reset to ‘0’ by writing a ‘1’ to the bit or, when unlatched current limitation handling has been enabled, the ILIM bit will be cleared when any of the six gate control driver outputs are activated.

Bit 3 – LDOF

LDO Failure Event Interrupt bit
ValueDescription
1 Any SIR2 register bits are set to ‘1’.
0 All of the SIR2 register bits are reset to ‘0’.

Bit 2 – OVTF

Overtemperature Failure Event Interrupt bit
ValueDescription
1 Any of the SIR4 register bits are set to ‘1’.
0 All of the SIR4 register bits are reset to ‘0’.

Bit 1 – VDSSC

Drain-Source Monitoring VDS Short Circuit Interrupt bit
ValueDescription
1 A VDS short circuit failure has been detected by at least one bit in SIR3[5:0] (at least one bit is set to ‘1’).
0 All of the bits in SIR3[5:0] are cleared.

Bit 0 – VGSUV

Gate-Source Monitoring VGS Undervoltage Interrupt bit
ValueDescription
1 A VGS undervoltage failure has been detected by at least one bit in SIR3[7:6] (at least one bit is set to ‘1’).
0 Both of the bits in SIR3[7:6] are cleared.