8.10.2.10 Programming and Debug Interface Configuration

The default value given in this fuse description is the factory-programmed value and may not be mistaken for the Reset value.

Name:	PDICFG
Offset:	0x0A
Reset:	0x0003
Property:	-


Bit	15	14	13	12	11	10	9	8
	KEY[11:4]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	KEY[3:0]						LEVEL[1:0]
Access	R/W	R/W	R/W	R/W			R/W	R/W
Reset	0	0	0	0			1	1

Bits 15:4 – KEY[11:0] NVM Protection Activation Key

This fuse bit field contains the 12-bit key used to enable NVM protection. After it is enabled, performing a chip erase is no longer possible. The protection is not enabled unless the device also has code protection enabled (the KEY bit field of the LOCK register set to the LOCKED state).

Value	Name	Description
Other	—	NVM protection not active. Chip erase is working.
0xB45	NVMACT	NVM protection active. Chip erase is disabled.

Bits 1:0 – LEVEL[1:0] UPDI Protection Level

This fuse bit field controls the level of UPDI protection.

Important: There is no way to recover from this mode; once NVMACCDIS is enabled, it is not possible to re-enable UPDI access for device programming. Ensure that the consequences of enabling this feature are fully understood before enabling this mode.

Warning: After activation of NVMACCDIS, advanced failure analysis will not be possible.

Value	Name	Description
Other	—	Reserved
0x2	NVMACCDIS	NVM access through UPDI is disabled. All erase and write commands to NVM must be executed from the Boot Code section (bootloader). Chip Erase and User Row writes are disabled. The CRC status remains available.
0x3	BASIC	The UPDI interface and UPDI pin function as normal. This is the default setting.