8.10.2.6 System Configuration 0

The default value given in this fuse description is the factory-programmed value and may not be mistaken for the Reset value.

Name:	SYSCFG0
Offset:	0x05
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	CRCBOOT	CRCSEL					BOOTROWSAVE	EESAVE
Access	R/W	R/W					R/W	R/W
Reset	0	0					0	0

Bit 7 – CRCBOOT Cyclic Redundancy Check (CRC) on Boot Section During System Initialization

This fuse bit controls whether the boot section of Flash is checked by the CRCSCAN peripheral during the Reset initialization. Refer to the CRCSCAN - Cyclic Redundancy Check Memory Scan chapter for more information about functionality.

Value	Name	Description
0x0	DISABLE	No CRC
0x1	ENABLE	CRC of the boot section

Bit 6 – CRCSEL CRC Polynomial Selection

This fuse bit controls the type of CRC performed by the CRCSCAN peripheral. Refer to the CRCSCAN - Cyclic Redundancy Check Memory Scan chapter for more information about the functionality.

Value	Name	Description
0x0	CRC16	CRC16 - CCITT
0x1	CRC32	CRC32 (IEEE 802.3)

Bit 1 – BOOTROWSAVE BOOTROW Saved During Chip Erase

This fuse bit controls whether the BOOTROW will be erased or preserved during a Chip Erase.

Value	Name	Description
0x0	DISABLE	The BOOTROW is erased during a Chip Erase
0x1	ENABLE	The BOOTROW is preserved during a Chip Erase regardless of whether the device is locked

Bit 0 – EESAVE EEPROM Saved During Chip Erase

This fuse bit controls whether the EEPROM is erased or preserved during a Chip Erase. If enabled, only the Flash memory will be erased by a Chip Erase.

Value	Name	Description
0x0	DISABLE	The EEPROM is erased during a Chip Erase
0x1	ENABLE	The EEPROM is preserved during a Chip Erase regardless of whether the device is locked