35.7 I/O Pins

Table 35-7. I/O Pin Specifications
Symbol Description Min. Typ.✝ Max. Unit Conditions
Input Low Voltage
VIL I/O PORT:
  • with Schmitt Trigger buffer
 — — 0.2×VDD V INLVL = 0
  • with TTL levels
 — < 0.8 — V

VDD > 2.7V

INLVL = 1
RESET pin — — 0.2×VDD V
Input High Voltage
VIH I/O PORT:
  • with Schmitt Trigger buffer
 0.8×VDD — — V INLVL = 0
  • with TTL levels
 — > 2.0 — V

VDD > 2.7V

INLVL = 1
RESET Pin 0.8×VDD — — V
Input Leakage Current(1)
IIL I/O PORTS — < 50 — nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C
RESET Pin(2) — <50 — nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C
Pull-up Resistance
RP — 26 — kΩ
Output Low Voltage
VOL Standard I/O ports — — — V IOL = 6 mA, VDD = 3.0V
Output High Voltage
VOH Standard I/O ports — — — V IOH = 6 mA, VDD = 3.0V
I/O Slew Rate
Rising slew rate — 45 — ns PORTCTRL.SRL = 0x01
Rising slew rate — 22 — ns PORTCTRL.SRL = 0x00
Falling slew rate — 30 — ns PORTCTRL.SRL = 0x01
Falling slew rate — 16 — ns PORTCTRL.SRL = 0x00
Pin Capacitance
CIO All I/O pins — 5 — pF

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Note:
  1. The negative current is defined as the current sourced by the pin.
  2. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may occur at different input voltages.