35.7 I/O Pins

Table 35-7. I/O Pin Specifications
Symbol	Description	Min.	Typ.✝	Max.	Unit	Conditions
Input Low Voltage
V_IL	I/O PORT:
with Schmitt Trigger buffer	—	—	0.2×V_DD	V	INLVL = `0`
with TTL levels	—	< 0.8	—	V	V_DD > 2.7V INLVL = `1`
RESET pin	—	—	0.2×V_DD	V
Input High Voltage
V_IH	I/O PORT:
with Schmitt Trigger buffer	0.8×V_DD	—	—	V	INLVL = `0`
with TTL levels	—	> 2.0	—	V	V_DD > 2.7V INLVL = `1`
RESET Pin	0.8×V_DD	—	—	V
Input Leakage Current⁽¹⁾
I_IL	I/O PORTS	—	< 50	—	nA	GND ≤ V_PIN ≤ V_DD, pin at high-impedance, T_A= 85°C
RESET Pin⁽²⁾	—	<50	—	nA	GND ≤ V_PIN ≤ V_DD, pin at high-impedance, T_A= 85°C
Pull-up Resistance
R_P		—	26	—	kΩ
Output Low Voltage
V_OL	Standard I/O ports	—	—	—	V	I_OL = 6 mA, V_DD = 3.0V
Output High Voltage
V_OH	Standard I/O ports	—	—	—	V	I_OH = 6 mA, V_DD = 3.0V
I/O Slew Rate
	Rising slew rate	—	45	—	ns	PORTCTRL.SRL = `0x01`
Rising slew rate	—	22	—	ns	PORTCTRL.SRL = `0x00`
Falling slew rate	—	30	—	ns	PORTCTRL.SRL = `0x01`
Falling slew rate	—	16	—	ns	PORTCTRL.SRL = `0x00`
Pin Capacitance
C_IO	All I/O pins	—	5	—	pF
✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only. Note: The negative current is defined as the current sourced by the pin. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may occur at different input voltages.

Input Low Voltage

V_IL

I/O PORT:

with Schmitt Trigger buffer

—

0.2×V_DD

V

INLVL = 0

with TTL levels

—

< 0.8

—

V

V_DD > 2.7V

INLVL = 1

RESET pin

—

0.2×V_DD

V

Input High Voltage

V_IH

I/O PORT:

with Schmitt Trigger buffer

0.8×V_DD

—

V

INLVL = 0

with TTL levels

—

> 2.0

—

V

V_DD > 2.7V

INLVL = 1

RESET Pin

0.8×V_DD

—

V

Input Leakage Current⁽¹⁾

I_IL

I/O PORTS

—

< 50

—

nA

GND ≤ V_PIN ≤ V_DD,

pin at high-impedance, T_A= 85°C

RESET Pin⁽²⁾

—

<50

—

nA

GND ≤ V_PIN ≤ V_DD,

pin at high-impedance, T_A= 85°C

Pull-up Resistance

R_P

—

26

—

kΩ

Output Low Voltage

V_OL

Standard I/O ports

—

V

I_OL = 6 mA, V_DD = 3.0V

Output High Voltage

V_OH

Standard I/O ports

—

V

I_OH = 6 mA, V_DD = 3.0V

I/O Slew Rate

Rising slew rate

—

45

—

ns

PORTCTRL.SRL = 0x01

Rising slew rate

—

22

—

ns

PORTCTRL.SRL = 0x00

Falling slew rate

—

30

—

ns

PORTCTRL.SRL = 0x01

Falling slew rate

—

16

—

ns

PORTCTRL.SRL = 0x00

Pin Capacitance

C_IO

All I/O pins

—

5

—

pF

✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Note:

The negative current is defined as the current sourced by the pin.
The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may occur at different input voltages.