35.17 ADC

Table 35-23. Power Supply, Reference and Input Range
Operating conditions:
  • VDD = 3.0V
  • TA = 25°C
  • Sample rate defined for SAMPDUR = 0x02 with ADC in Free-Running mode
  • Applies for all allowed combinations of VREF selections and sample rates, unless otherwise specified
  • Characteristics are identical with and without PGA enabled, unless otherwise specified
Symbol Description Min. Typ.✝ Max. Unit Conditions
VDD Supply voltage 1.8 — 5.5 V
VREF Reference voltage 1.024 — VDD V
CIN Input capacitance — 2.5 — pF PGA disabled
— 7 — PGA enabled
RIN Input resistance — 3 — kΩ PGA disabled
— 2.5 — kΩ PGA enabled
VIN Input voltage range 0 — VREF V Single-ended mode
-0.1 — VDD + 0.1 Differential mode

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.
Table 35-24. Clock and Timing Characteristics
Operating conditions:
  • VDD = 3.0V
  • TA = 25°C
  • Sample rate defined for SAMPDUR = 0x02 with ADC in Free-Running mode
  • Applies for all allowed combinations of VREF selections and sample rates, unless otherwise specified
  • Characteristics are identical with and without PGA enabled, unless otherwise specified
Symbol Description Min. Typ.✝ Max. Unit Conditions
CLK_ADC ADC clock frequency 300 — 2000 kHz REFSEL = Internal Reference
300 — 6000

REFSEL = External Reference

REFSEL = VDD

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.
Table 35-25. Accuracy Characteristics
Operating conditions:
  • VDD = 3.0V
  • VDD = VREF
  • TA = 25°C
  • fCLK_ADC = 2 MHz
  • Sample rate defined for SAMPDUR = 0x02 with ADC in Free-Running mode
  • Applies for all allowed combinations of VREF selections and sample rates, unless otherwise specified
  • Characteristics are identical with and without PGA enabled, unless otherwise specified
Symbol Description Min. Typ.✝ Max. Unit Conditions
Res Resolution — — 12 bit
EINL Integral nonlinearity — 0.8 — LSb

VDD = 3.0V
VREF = 2.048V
CLK_ADC = 2.5 MHz
Differential mode
EDNL Differential nonlinearity — 0.8 —
EOFF Offset error — 1.5 —
EGAIN Gain error — 0.6 —
ET Total unadjusted error — 5 —

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.
Table 35-26. Accuracy Characteristics with PGA Enabled
Operating conditions:
  • VDD = 3.0V
  • -40°C ≤ TA ≤ 125°C
  • Sample rate defined for SAMPDUR = 0x02 with ADC in Free-Running mode
  • Applies for all allowed combinations of VREF selections and sample rates, unless otherwise specified
  • Characteristics are identical with and without PGA enabled, unless otherwise specified
Symbol Description Min. Typ.✝ Max. Unit Conditions
NRMS Input noise — 32 — µVRMS PGA Gain = 1V/V
— 63 — PGA Gain = 2V/V
— 125 — PGA Gain = 4V/V
— 250 — PGA Gain = 8V/V
— 500 — PGA Gain = 16V/V
EGAIN Gain error — -0.2 — % PGA Gain = 1V/V
— -0.2 — PGA Gain = 2V/V
— -0.3 — PGA Gain = 4V/V
— -0.6 — PGA Gain = 8V/V
— -0.8 — PGA Gain = 16V/V

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.