35.4 Supply Voltage

Table 35-4. Supply Voltage
SymbolMin.Typ. ✝Max.UnitsConditions
Supply Voltage
VDD1.62(1)—5.5V
RAM Data Retention(2)
VDR1.62——V
Power-on Reset Release Voltage(4)
VPOR—1.51.62VBOD disabled(3)
Power-on Reset Re-Arm Voltage(4)
VPORR—1.1—VBOD disabled(3)
VDD Slope(5)
SVDD——0.2V/µsBOD disabled(3)

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified, . These parameters are not tested and are for design guidance only.

Note:
  1. Operation is ensured down to 1.62V or BOD triggering level VBOD when BOD is active.
  2. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
  3. Refer to RSTCTRL and BOD for BOD trip point information.
  4. Refer to Figure 35-1.
  5. For design guidance only and not tested in production.
Figure 35-1. POR and PORR with Slow Rising VDD
Note: When POR is low, the device is held in Reset.