35.14 SPI

Figure 35-6. SPI - Timing Requirements in Host Mode

Table 35-18. SPI - Timing Specifications in Host Mode
Symbol	Description	Min.	Typ. ✝	Max.	Units
f_SCK⁽¹⁾	SCK clock frequency	—	—	f_{CLK_PER}/2	MHz
T_SCK⁽¹⁾	SCK period	2×T_{CLK_PER}	—	—	ns
t_SCKW	SCK high/low width	—	0.5×T_SCK	—	ns
t_MOS	MOSI valid before SCK	—	0.5×T_SCK	—	ns
t_MOH	MOSI hold after SCK	—	0.5×T_SCK	—	ns
t_MIS	MISO setup to SCK	—	T_{CLK_PER}	—	ns
t_MIH	MISO hold after SCK	—	0	—	ns
✝ Data in the “Typ.” column is measured at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only. Note: These parameters are characterized but not tested in production.

Figure 35-7. SPI - Timing Requirements in Client Mode

Table 35-19. SPI - Timing Specifications in Client Mode
Symbol	Description	Min.	Typ. ✝	Max.	Units	Conditions
f_SSCK⁽¹⁾	Client SCK clock frequency	—	—	f_{CLK_PER}/6	MHz
T_SSCK⁽¹⁾	Client SCK period	6×T_{CLK_PER}	—	—	ns
t_SSCKW⁽¹⁾	SCK high/low width	3×T_{CLK_PER}	—	—	ns
t_SIS⁽¹⁾	MOSI setup to SCK	0	—	—	ns
t_SIH⁽¹⁾	MOSI hold after SCK	3×T_{CLK_PER}	—	—	ns
t_SSS⁽¹⁾	SS low before SCK	—	T_{CLK_PER}	—	ns
t_SSH⁽¹⁾	SS high after SCK	—	T_{CLK_PER}	—	ns
t_SOS	MISO Valid after SCK	—	t_SR⁽²⁾	—	ns
t_SOSS	MISO setup after SS low	—	t_SR⁽²⁾	—	ns
t_SOSH	MISO hold after SS high	—	t_SR⁽²⁾	—	ns
t_SDLY	Interbyte delay	5 - f_{CLK_PER}/(2*f_SSCK)	—	—	ns	f_SSCK<f_{CLK_PER}/10
t_SDLY	Interbyte delay	0	—	—	ns	f_SSCK≥f_{CLK_PER}/10
✝Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only. Note: These parameters are characterized but not tested in production. t_SR is the I/O pin rise/fall time.