35.19 UPDI

Figure 35-9. UPDI Enable Sequence with Dedicated UPDI Pin

Table 35-27. UPDI Timing Specifications
Symbol	Description	Min.	Max.	Unit	Conditions
t_RES ^*	Duration of Handshake/Break on RESET	10	200	µs
t_UPDI ^*	Duration of UPDI.txd = 0	10	200	µs
t_Deb0^*	Duration of Debugger.txd = 0	0.2	1	µs
t_DebZ^*	Duration of Debugger.txd = z	200	14000	µs
f_UPDI ^*	UPDI clock frequency	—	4	MHz	V_DDMIN ≤ V_DD ≤ V_DDMAX	T_{A_MIN} ≤ T_A ≤ T_{A_MAX}
		—	8	MHz	2.7V ≤ V_DD ≤ 5.5V
		—	16	MHz	4.5V ≤ V_DD ≤ 5.5V
		—	8	MHz	V_DDMIN ≤ V_DD ≤ V_DDMAX	0ºC ≤ T_A ≤ +50ºC
		—	16	MHz	2.7V ≤ V_DD ≤ 5.5V
		—	32	MHz	4.5V ≤ V_DD ≤ 5.5V
* These parameters are for deign guidance only and are not tested.

Figure 35-10. UPDI Enable Sequence by High-Voltage (HV) Programming

Table 35-28. UPDI HV Pulse Specifications
Symbol	Description	Min.	Typ.	Max.	Unit
V_HV ^*	Debugger RESET HV signal level	V_DD+2	7.5	8.5	V
T_HV ^*	Debugger RESET HV signal duration	10	—	—	µs
T_{UPDI_TIMEOUT} ^*	Time to receive valid key after HV pulse	—	65	—	ms
* These parameters are for design guidance only and are not tested.