5.5 Configure SPI Packet
The Configure SPI Packet configures the SPI settings for a single chip select channel as part of the packet sequence. Unlike the Peripherals SPI section, which uses tabs for CS0–CS3, this packet includes a Chip Select drop-down to select which channel to configure.
| Field | Description | Validation |
|---|---|---|
| Chip Select | The SPI chip select channel to configure (CS0–CS3) | Drop-down selection |
| Speed | The SPI clock speed | Predefined speed options |
| Mode | The SPI mode (clock polarity and phase) | Predefined mode options |
| Active Low/Active High | The chip select polarity, with a small waveform preview | Toggle between the two states |
| CS/Data Delay | A delay, in microseconds, between chip select assertion and data transfer (0–5000 μs) | Integer from 0 to 5000 μs |
The CS/Data Delay field displays a validation icon:
| Icon State | Tooltip | Notes |
|---|---|---|
| Editing | “Click to validate CS/Data delay.” | Shown while the user is editing the field |
| Error | “CS/Data delay must be a positive value, up to 5000 μs, in increments of 1 μs.” | Shown after validation finds errors |
Fastpath: Pressing <Enter> or clicking away from the field triggers validation.