20.2.3.2 EJTAG Control Register
| Name: | ECR: EJTAG Control Register |
| Offset: | 0x30 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Rocc | Psz[1:0] | ||||||||
| Access | R/W | R | R | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VPED | Doze | Halt | PerRst | PrnW | PrACC | PrRst | |||
| Access | R | R | R | R | R | R/W | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ProbEn | ProbTrap | EjtagBrk | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DM | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 31 – Rocc
Note: For descriptions of these bits, refer to the Imagination
Technologies Limited (www.imgtec.com).
Bits 30:29 – Psz[1:0]
Note: For descriptions of these bits, refer to the
Imagination Technologies Limited (www.imgtec.com).
Bit 23 – VPED
Note: For descriptions of these bits, refer to the
Imagination Technologies Limited (www.imgtec.com).
Bit 22 – Doze
Note: For descriptions of these bits, refer to the
Imagination Technologies Limited (www.imgtec.com).
Bit 21 – Halt
Note: For descriptions of these bits, refer to the
Imagination Technologies Limited (www.imgtec.com).
Bit 20 – PerRst
Note: For descriptions of these bits, refer to the
Imagination Technologies Limited (www.imgtec.com).
Bit 19 – PrnW
Note: For descriptions of these bits, refer to the
Imagination Technologies Limited (www.imgtec.com).
Bit 18 – PrACC Pending Processor Access and Control bit
This bit indicates a pending processor access and controls finishing of a
pending processor access. A write of ‘0’ finishes processor
access if pending. A write of ‘1’ is ignored. A successful
FASTDATA access clears this bit.
| Value | Description |
|---|---|
| 1 | Pending processor access |
| 0 | No pending pre-processor access |
Bit 16 – PrRst
Note: For descriptions of these bits, refer to the
Imagination Technologies Limited (www.imgtec.com).
Bit 15 – ProbEn Processor Access Service Control bit
This bit controls where the probe handles accesses to the DMSEG segment through servicing of processor accesses.
| Value | Description |
|---|---|
| 1 | A BCFG error has occurred |
| 0 | A BCFG error has not occurred |
Bit 14 – ProbTrap Debug Exception Vector Control Location bit
This bit controls the location of the debug exception vector.
| Value | Description |
|---|---|
| 1 | 0xFF200200 |
| 0 | 0xBFC00480 |
Bit 12 – EjtagBrk Debug Interrupt Exception Request bit
This bit requests a debug interrupt exception to the processor when this bit is written as ‘1’. A write of ‘0’ is ignored.
| Value | Description |
|---|---|
| 1 | A debug interrupt exception request is pending |
| 0 | A debug interrupt exception request is not pending |
Bit 3 – DM
Note: For descriptions of these bits, refer to the
Imagination Technologies Limited (www.imgtec.com).