20.2.3 ETAP Control (ETAP_CONTROL)
Command
ETAP_CONTROL selects the Control register. The EJTAG Control Register
(ECR) handles processor Reset and soft Reset indication, Debug mode indication, access
start, finish and size and read/write indication. The ECR also provides the following
features:
- Controls debug vector location and indication of serviced processor accesses
- Allows a debug interrupt request
- Indicates a processor Low-power mode
- Allows implementation-dependent processor and peripheral Resets