20.2.3.1 EJTAG Control register (ECR)

The EJTAG Control register (see ECR: EJTAG Control Register) is not updated/written in the Update-DR state unless the Reset occurred; that is ROCC (bit 31) is either already ‘0’ or is written to ‘0’ at the same time. This condition ensures proper handling of processor accesses after a Reset.

Reset of the processor can be indicated through the ROCC bit in the TCK domain a number of TCK cycles after it is removed in the processor clock domain in order to allow for proper synchronization between the two clock domains.

Bits that are Read/Write (R/W) in the register return their written value on a subsequent read, unless other behavior is defined.

Internal synchronization ensures that a written value is updated for reading immediately afterwards, even when the TAP controller takes the shortest path from the Update-DR to Capture-DR state.