In 2-phase ICSP™ mode, the TMS and TDI device pins are multiplexed
into PGEDx in two clocks, see Figure 5-5. The LSb is shifted
first; and TDI and TMS are sampled on the falling edge of PGECx. There is no TDO output
provided in this mode. The 2-phase ICSP mode was designed to accelerate Two-Wire,
write-only transactions.
Note: The packet is not actually executed
until the first clock of the next packet. To enter Two-Wire, 2-phase ICSP mode, the
TDOEN bit (DDPCON[0] or CFGCON[0]) must be set to ‘0’.
Figure 5-5. Two-Wire and 2-Phase
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