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40.7.8 Channel Configuration3 (SIGN/DIFF)
Table 40-14. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: CHNCFG3 Offset: 0x02C Reset: 0x00000000 Property: RW
Bit 31 30 29 28 27 26 25 24 SIGN SIGN SIGN SIGN SIGN SIGN SIGN SIGN Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 SIGN SIGN SIGN SIGN SIGN SIGN SIGN SIGN Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – SIGN SIGN setting When set to 1, the
associated channel x will have its output converted data in signed format.
Otherwise, the output data will be in unsigned format.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – DIFF Differential Mode When set, the
associated channel x is connected in differential mode. Otherwise, this channel is
connected in single-ended mode.
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Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – SIGN SIGN setting Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – DIFF Differential Mode
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