40.7.21 CORE Controller Interrupt Enable Clear

Note: Writing a zero to these bits has no effect. Writing a one to these any of these bits will CLEAR the ENABLE bit.

Note: A read of this register provides whether the Interrupt is Enabled (bit=1) or Disabled (bit=0), i.e. a write of a 1 to the bit then a read of the bit will return the interrupt is disabled (=0).

Table 40-27. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CTLINTENCLR
Offset:	0x100
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					PFFHFUL	PFFRDY	PFFOVF	PFFUNF
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	VREFRDY	VREFUPD						CRRDY0
Access	R/W	R/W						R/W
Reset	0	0						0

Bit 11 – PFFHFUL APB FIFO Half Full

Writing a 1 to this bit will disable the ADC FIFO Half Full as an interrupt request.

Reading this bit returns whether the PFFHFUL interrupt is enabled (1 = enabled).

Bit 10 – PFFRDY APB FIFO Ready

Writing a 1 to this bit will disable the ADC FIFO Data Ready as an interrupt request.

Reading this bit returns whether the PFFRDY interrupt is enabled (1 = enabled).

Bit 9 – PFFOVF APB FIFO overflow

Writing a 1 to this bit will disable the ADC FIFO Overflow Error as an interrupt request,

Reading this bit returns whether the PFFOVF interrupt is enabled (1 = enabled).

Bit 8 – PFFUNF APB FIFO underflow

Writing a 1 to this bit will disable the ADC FIFO Read Underflow Error as an interrupt request.

Reading this bit returns whether the PFFUNF interrupt is enabled (1 = enabled).

Bit 7 – VREFRDY VREF Ready

Writing a 1 to this bit will disable the ADC Voltage Reference Ready as an interrupt request.

Reading this bit returns whether the VREFRDY interrupt is enabled (1 = enabled).

Bit 6 – VREFUPD VREF Update

Writing a 1 to this bit will disable the ADC Voltage Reference Ready Updated as an interrupt request.

Reading this bit returns whether the VREFUPD interrupt is enabled (1 = enabled).

Bit 0 – CRRDYx Core Ready x Disable

Writing a 1 to this bit will disable the Core x (where x is up to 0) Ready as an interrupt request.

Reading this bit returns whether the CRRDYx interrupt is enabled (1 = enabled).