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40.7.6 Channel Configuration 1 (LVL/CMPEN)
Table 40-12. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: CHNCFG1 Offset: 0x024 Reset: 0x00000000 Property: RW
Bit 31 30 29 28 27 26 25 24 LVL LVL LVL LVL LVL LVL LVL LVL Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 LVL LVL LVL LVL LVL LVL LVL LVL Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN CHNCMPEN Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – LVL Channel Level Channel x is
sensitive to the high level of its trigger. Otherwise it is sensitive only to the
positive edge of its trigger.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – CHNCMPEN Channel Comparator Enable Channel x is being
monitored by the Digital Comparator which is servicing this channel. Otherwise, this
channel will not be monitored by the Digital Comparator.
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Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – LVL Channel Level Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – CHNCMPEN Channel Comparator Enable
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