2.3 High-speed I/O Clock Networks

High-speed I/O clock networks are low-skew high-speed clocks distributed along the edge of the device to service the I/Os. High-speed I/O networks are used to clock data in and out of the I/O logic when implementing the high-speed I/O interfaces. There are no high-speed I/O clock networks located on the east side of the FPGA fabric. Each I/O bank has six high-speed I/O clocks. High-speed I/O clocks from adjacent banks on the same edge can be bridged to build large I/O interfaces.

High-speed I/O clock networks can be driven from I/Os or CCCs. The high-speed I/O clocks can feed reference clock inputs of adjacent CCCs through hardwired connections.

The CCC can be configured to have a PLL or DLL clock output driving a high-speed I/O clock network. The I/Os support specific I/O interface modes (for example, DDRxn modes) that are designed to use the high-speed I/O clock networks. When using I/O interface modes that support high-speed I/O clock networks, the Libero SoC automatically routes the clocks coming from I/O lanes on the high-speed I/O clock networks. For more information about high-speed I/O clock networks, see PolarFire Family I/O User Guide.