2.9 Global Net Clock Jitter

Global clock networks are susceptible to clock jitter induced by a design-specific simultaneous switching activity and the response of an internal device and board-level Power Distribution Network (PDN).

There are two distinct contributors to increased clock jitter:

  • The PDN's inability to meet the large transient current demands under extreme design toggle rates. This can occur regardless of the clock frequencies in the user design.
  • Design operation with a large amount of logic toggling simultaneously at the PDN resonance frequency, which typically ranges from 10 MHz to 40 MHz, depending on the specific board design. Depending on the aggressor clock frequency, either one of these two effects at a time can contribute to increased global net clock jitter.

The aggressor clock domain can induce jitter on unrelated victim clock domains. Therefore, the victim clock domains must also consider global net clock jitter. To address the first contributor, the PolarFire core voltage supply (VDD) must always be maintained in accordance with the data sheet specifications at the device package pins, during design operation. The operating voltage specification includes the regulator DC variation plus any power supply ripple over the customer design frequencies, as measured at the device package pins. For information about operating voltage specification, see the respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet . The VDD ripple during design operation can be measured for specific designs and boards to ensure that it conforms to the data sheet specifications.

Typically, designs operate with a continuous noise floor and a relatively low simultaneous Flip-Flop (FF) toggle rate, which helps to spread the current demand over time. However, designs with abnormally high toggle rates, greater than 25% of the total device FFs toggling simultaneously in the same direction, increase the instantaneous current demand on the VDD supply. Furthermore, if that large quantity of simultaneously switching FFs periodically starts and stops with a low enable rate, it can cause a large transient current demand on the PDN as the logic is re-enabled. Depending on the amount of fabric logic that starts toggling simultaneously when the enable is asserted, the transient current demand on the PDN can cause the VDD to dip below the data sheet limits. To avoid extra global net clock jitter, ensure that the VDD is always maintained within the data sheet limits during design operation.

Regarding the second contributor to global net clock jitter, it is related to the utilization percentage of the FFs in the device that toggle simultaneously, in the same direction, at a given clock edge, when the clock domain operates within the 10 MHz to 40 MHz range. In typical designs, the average FF toggle rate per clock domain does not exceed ~25%. Specific boards and designs might require higher toggle rates, but support for that level of operation must be confirmed by design-specific VDD variation and clock jitter measurements taken on the user board with the design operating at its maximum switching activity.

For information about maximum period jitter specifications on the PolarFire Global Network for various FF toggle rates within the device, see the respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet . This specification on PolarFire global net clock jitter is a worst-case maximum period jitter that applies across the supported silicon process, voltage, and temperature range.

Libero SoC v2022.1 and later design software flow has an enhanced capability that automatically analyzes, applies clock uncertainty constraints, and accounts for global net clock jitter during Layout and Static Timing Analysis (STA). The software clock jitter algorithms used during timing-driven Place & Route optimize and compensate for known clock jitter components of the design. This process generates a Timing Analysis Jitter Report that details the jitter calculated to clock domains. Clock uncertainty constraints can also be modified, and user additive constraints can be specified for external sources. For information, see Timing Constraints Editor User Guide .