2.1 Global Clock Network

The global clock network is used to distribute high fan-out signals such as clocks and resets across the FPGA fabric with low-skew, using a vertical and horizontal clock stripe architecture.

The following figure shows the global clock network architecture and the possible clocks that are routed on the network. Two vertical clock stripes are positioned at approximately one quarter and three quarters of the FPGA fabric width. A horizontal clock stripe runs across the middle of the FPGA fabric.

The global clock network can be driven by any of the following:

  • Preferred clock inputs (CLKIN_z_w)
  • On-chip oscillators
  • CCC (PLL/DLL)
  • Fabric routed signals
  • Clock dividers
  • NGMUXs
  • Transceiver interface clocks
Important: Only one global clock is supported per transceiver quad. For more information about the performance of the global clock for the transceiver quads, see the respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet .
Figure 2-1. Global Clock Network and Clock Sources

The global clock network is composed of Global Buffers (GBs) for clock distribution. As shown in the following figure, there are 48 GBs—24 GBs distribute clocks to the left half of the fabric and the remaining 24 GBs distribute clocks to the right half through vertical clock stripes.

Each GB drives an independent half-chip global clock (GCLK). Two GBs—one from each half—are instantiated by the Libero SoC to distribute a clock to the entire FPGA fabric. A design can have a maximum of 24 full-chip global signals or 48 half-chip global signals. Up to 24 fabric routed signals can drive the half-chip globals.

Clocks driven from regular I/Os, internally generated clocks, and high fan-out signals, such as resets can be routed to GBs using a CLKINT macro.

Figure 2-2. FPGA Fabric—Global Clock Routing Architecture

Each GB drives Row Global Buffers (RGB) present on the vertical clock stripes to reach the logic sectors. Each RGB selects a global clock, regional clock, or fabric routed clock to drive the logic sectors located on the left or right side of the vertical clock stripe.

As shown in Figure   2, the logic clusters are organized in a repeated pattern of sectors. A row of sectors is divided into four quarters. Each sector consists of six logic-cluster columns and nine logic-cluster rows including two Math blocks, two LSRAM blocks, and six µSRAM blocks, as shown in the following figure. Each logic-cluster contains 12 Logic Elements (LE), each LE consisting of a four-input LUT and D flip-flop.

Figure 2-3. Sector Representation

A set of 18 RGBs drive each quarter of every row of sectors on both sides of the vertical stripe. Each RGB generates a row global clock (RGCLK). Two RGBs—one from either side—must be driven from the same clock source to distribute the clock in both directions, to serve a region of half-row sectors. Up to eight fabric routed signals can drive the RGB resources that serve a half-row of sectors.

Each global and row global buffer has a gating option for glitch-free enabling and disabling of the clock, for more information, see Clock Gating. Up to seven fabric routed signals can gate the RGB resources that serve a half-row of sectors.

A RCLKINT or RGCLKINT macro is used to drive the RGB to create a local clock spanning a small fabric area.

If users do not specify the global clock network assignments, then synthesis tools assign a clock network based on the predetermined priorities. These priorities are primarily set by the fan-out of each signal. Synthesis tools attempt to assign the low-skew resources to clock signals with high fan-out. To improve the performance, users can take control of the clock network assignment by instantiating the required macros or attributes in the design. For a list of macros supported in the PolarFire family, see Clock Macros.

If there are more than 24 global clock signals in the design, the Libero SoC creates half-chip global clocks and splits the placement of the logic accordingly.