2.2 Regional Clock Networks

Regional clock networks exhibit lower latency than the global clock network. They comprise regional clock buffers (RCBs) that interface with the I/O and transceiver lanes at regular intervals as follows:

  • One regional clock buffer per I/O lane (a grouping of 12 I/Os) on the north, south, and west edges.
  • Two regional clock buffers per transceiver lane (eight per transceiver quad) on the east edge.

A regional clock buffer can be driven from either an I/O lane or the transceiver lane. The nets driven by the regional clock buffers are referred to as regional clocks (RCLKs). The following figure shows the location of the regional clock buffers.

Figure 2-4. Regional Clock Buffers

Each regional clock buffer drives all the RGBs present within its region to distribute the clock. Each regional clock buffer serves a region of a fixed number of sectors. The region size depends on the location of the regional clock buffer and transceiver quad capabilities. The regions cover the entire fabric without overlapping. Regional clocks cannot be aggregated to span large regions. If a clock is required to span multiple regions, then a GCLK must be used.

Each regional clock buffer on the north and south edge serves a quadrant of the FPGA fabric. The following figure shows the region served by the regional global buffers using the bottom-right corner of the FPGA fabric as an example.

Figure 2-5. Regional Clock Buffer Fan-outs from Bottom-Right I/O Lanes

Each regional clock buffer on the west and east edge serves a region as high as two transceiver quads and half the width of the FPGA fabric. The region size is six half-row sectors if the quads are without PCIe® controllers. The region size is eight half-row sectors, if one of the quads has PCIe controllers. The following figure shows the region served by the regional clock buffers from a transceiver lane. For more information about region resource details, see PolarFire Family Transceiver User Guide.

Figure 2-6. Regional Clock Buffer Fan-outs from Transceiver

The PolarFire family offers up to 101 regional clock buffers to move data in and out of the fabric.

The transceiver interface is configurable to have the lane clocks (TX_CLK and RX_CLK) routed on regional or global clock networks. The I/Os support specific I/O interface modes (for example, DDRxn modes) that are designed to use regional clocks. For more information on I/O interface modes, see the I/O Interface Modes section of PolarFire Family I/O User Guide. When using the I/O interface modes that support regional clocks, Libero SoC automatically routes clocks coming from I/O lanes on the regional clock networks.