2.6 Clock Gating

Each global and row global buffer has a gating option for glitch-free enabling and disabling of the clock. The clock-gating enable port driven from the fabric logic can be changed dynamically. The clock gating feature is accessible by instantiating a clock buffer macro (GCLKINT or RGCLKINT) in the design. The GCLKINT macro provides clock gating at the global buffer level, and the RGCLKINT macro provides clock gating at the row global buffer level. The following figure shows a schematic of the clock-gating circuit.

Clock gating is achieved using a latch and enable (EN) that is driven by the user logic implemented in the FPGA fabric. The latch is transparent when the clock input is in the low phase. The latch is in a Hold state when the clock is in the high phase. The AND gate at the output allows enabling or disabling of the clock based on the latch output. The clock is active when the EN signal is HIGH, and it is gated off and driven LOW when the EN signal is LOW.

The following figure shows the timing waveforms for buffers with clock gating enabled. For the minimum setup and hold time for the clock gating enable signal, see the respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet .

• If the EN signal changes during the clock high phase and the minimum hold time is met with respect to the prior rising clock edge, then the latch output changes after the falling clock edge.
• If the EN signal changes during the clock low phase and the minimum setup time is met with respect to the next rising clock edge, then the latch output changes immediately.
• If the EN signal violates either the setup or hold time with respect to the rising clock edge, then the output behavior is unknown.

For falling-edge clocks, the EN signal must arrive by the prior rising edge (earlier than usual). Unused global resources such as RGBs and GBs are tied off automatically to reduce dynamic power consumption.