2.4 Preferred Clock Inputs
(Ask a Question)Preferred clock input I/Os connect external clock signals to the CCCs and/or the global clock network through low-latency paths. Use these preferred clock inputs for connecting external clocks to the clock inputs of PLLs, DLLs, and fabric logic. Using regular I/Os as clock inputs introduces high latency on the path.
Each preferred clock input can be used either as a single-ended clock input or be paired with an adjacent I/O to form a differential clock input. Preferred clock inputs, if not utilized for clocking, can be used as regular I/Os.
Preferred clock inputs are located on the north, south, and west sides of the device, with eight on the west side, 12 on the north side, and either 12 or 16 on the south side, depending on the package and device type as shown in the following figure. Some of the preferred clock inputs have access to both CCC and the global clock network and can be connected to either of them.
