2.5 Interface Clock Block

Interface Clock Block (ICB) multiplexes clock inputs from various clock sources (CCCs, preferred clock inputs, High-Speed I/O network, Oscillators, and FPGA fabric) and provides an entry into the global clock network. The east and west edges of the device have one ICB each. The north and south edges of the core have two ICBs each. Each ICB contains four clock dividers, two no-glitch clock multiplexers (NGMUXs), 12 clock gating circuits, and clock routing multiplexers to route clocks. Each ICB has two ICB_INT cells and 12 ICB_CLKINT cells. The ICB_INT cells are needed to route clocks from fabric to ICB. ICB_CLKINT cells are needed to route clocks from ICB to global buffers. If you encounter the limitation of the number of ICB_INT cells per ICB, use dedicated connections from CCCs, preferred clock inputs, and oscillators, which do not require ICB_INT cells. The following sections describe the clock dividers and NGMUXs present in the ICBs.