4.7 CCC Simulation Support

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Microchip Libero SoC provides pre-compiled simulation models for the CCC to show the functional behavior of the fabric CCC. The simulation steps include generating the top-level component, which instantiates CCC, performing simulation for verification with the ModelSim® tool, and performing static timing analysis with SmartTime in the Libero SoC.

Important:

CCC simulation in post-divider mode does not work if POWERDOWN input is not driven or tied high.
PLL is a fast simulation model and does not mimic the exact silicon behavior. The lock in simulation always comes after a fixed number of Phase Frequency Detector (PFD) cycles.