4.4 Delay-Locked Loops

DLLs can be used in a wide range of applications, such as precise phase-shifted clock generation, clock insertion delay removal, phase reference delay (for 90° phase shift), and duty-cycle correction. DLLs add delay to the reference clock to create specific phase relationships. There are two types of DLL outputs—clock signals (CLK_0 and CLK_1) and a delay code vector (CODE[7:0]).

Figure 4-13. DLL Block Diagram

The key blocks of a DLL are PFD, arithmetic logic unit (ALU), and a delay chain including five delay cells with 128 delay taps each. Each delay tap is designed for a delay of ~25 ps steps. For characterized values, see the respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet . The delay taps are not PVT compensated.

The reference clock must be sourced from one of the following:

  • Preferred clock inputs
  • High-speed I/O clocks
  • FPGA fabric routed clocks
  • Transceiver interface clocks (CCC_SE only)
Note: The preferred clock inputs which are capable of driving CCCs have dedicated connections to clock inputs (reference clock or feedback clock) of PLLs and/or DLLs present in the CCCs. For the connectivity of preferred clock inputs to PLLs and DLLs present in a CCC, see Preferred Clock Inputs Connectivity in CCCs.

The reference clock feeds the delay chain block and PFD. The reference clock can be divided before it is fed to the PFD.

The PFD detects the phase difference between the reference clock and the feedback clock, and produces an up or down signal to the ALU. The ALU increments or decrements the number of delay taps utilized by the delay cells until the rising edges of the feedback clock align with the reference clock. After the two clocks are in phase, the DLL is locked and the LOCK signal is asserted, thereby compensating for the delay in the clock distribution path. The phase lock range has four options to accommodate various cycle-to-cycle jitter tolerance requirements: ±200 ps–400 ps, ±350 ps–700 ps, ±500 ps–1000 ps, and ±750 ps–1500 ps.

The duty-cycle correction feature of DLLs corrects the duty cycle of the reference clock to create a 50% duty-cycle clock output. Clocks with a 50% duty cycle are important for implementing high-speed communication interfaces (for example, DDR applications).