4.3 Phase-Locked Loops

PLLs are used in a variety of clock management applications, such as clock phase adjustment, jitter filter, and frequency synthesis. For systems where Electromagnetic Interference (EMI) is a significant factor, PLLs offer spread-spectrum capabilities to minimize the EMI. The following figure shows the PLL block diagram.

For RT PolarFire devices, the user must review the project-specific reliability requirements and the relevant Radiation Test Report corresponding to the intended operating environment. Reviewing the RT PolarFire radiation test reports for PLL upset rates in Heavy Ion (GEO) versus Proton (LEO) environments helps the user decide whether the CCC PLL can be used for the specific project requirements. The Heavy Ion PLL results are found in RT PolarFire® Heavy Ion Radiation Single Event Effect Test Report LBNL June 5, 2021. The Proton PLL results are found in the PolarFire Proton Radiation Test Report CNL Oct 17, 2018. RT PolarFire devices enable high-speed payload data path applications, as opposed to spacecraft control logic, for which RTG4™, RTAX™-S/DSP, and RTSX-SU FPGAs are better suited. It is a payload application-dependent decision whether the system tolerates the PLL upset rates in the test reports and the corresponding system-level impact, such as pauses or gaps in the data stream.

The following information is provided as a brief summary of PolarFire heavy-ion and proton test reports:

• Heavy-Ion: According to the RT PolarFire heavy ion test report, there are PLL loss of lock events at low LET levels that do not self-recover. In general, a user might decide to use the RTPF fabric CCC PLL in applications where loss of lock events occurring at the upset rates described in the test reports can be tolerated, where the clock is stopped until the user design can reset the PLL and re-acquire lock. The PF_CCC core does not include auto-reset logic to handle PLL loss of lock. Therefore, to react to a radiation-induced loss of lock, the user can add fabric logic to monitor the PLL lock output. The user logic would detect the loss of lock, gate off the clocks, toggle the PLL_POWERDOWN_N input to reset the PLL, then re-enable the gated clocks after the PLL has re-acquired lock. For more information on two methods to perform glitch-free clock gating using either the CCC Clock Output mode called Global Clock (Gated) or the glitch-free start and stop feature controlled by OUT#_EN, see Clock Start/Stop Input and CCC Configuration sections. The CCC clock output mode using Global Clock (Gated) provides access to the Clock Gating feature, which is described in Clock Gating.
• Proton: According to the PolarFire proton test report, there were zero PLL loss of lock events observed. The user must review whether this data is relevant for their mission environment, such as a LEO application, and then design with the PolarFire CCC/PLL as desired.