4.1 Features

Each CCC supports the following features:

• Two fractional PLLs, each supporting:
  • Integer or fractional mode
  • Dual-reference clock inputs with manual switchover
  • Four independent clock outputs
  • Phase selection and adjustment
  • Programmable delay cells
  • Internal feedback mode for low jitter
  • De-skew mode with external feedback clock input
  • Programmable bandwidth control
  • Spread-spectrum clock generation
  • Glitch-free start/stop operations for clock outputs
  • Power-down mode
• Two DLLs, each supporting:
  • Two independent clock outputs
  • Variable phase shift selection
  • Duty-cycle correction
  • Delay code generation
  • Clock division
  • Power-down mode
• PLL and DLL cascading