6 Resets

This data sheet summarizes the features of the dsPIC33CK512MP608 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Reset” (www.microchip.com/DS70602).

The Reset module combines all Reset sources and controls the device Reset Signal, SYSRST. The following is a list of device Reset sources:
  • POR: Power-on Reset
  • BOR: Brown-out Reset
  • MCLR: Master Clear Pin Reset
  • SWR: RESET Instruction
  • WDTO: Watchdog Timer Time-out Reset
  • CM: Configuration Mismatch Reset
  • TRAPR: Trap Conflict Reset
  • IOPUWR: Illegal Condition Device Reset
    • Illegal Opcode Reset
    • Uninitialized W Register Reset
    • Security Reset

A simplified block diagram of the Reset module is shown in Figure 6-1.

Figure 6-1. Reset System Block Diagram

Any active source of Reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state, and some are unaffected.

Note: Refer to the specific peripheral section or “Memory Organization” of this data sheet for register Reset states.

All types of device Reset set a corresponding status bit in the RCON register to indicate the type of Reset.

A POR clears all the bits, except for the BOR and POR bits (RCON[1:0]) that are set. The user application can set or clear any bit, at any time, during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur.

The RCON register also has other bits associated with the Watchdog Timer and device Power-Saving states. The function of these bits is discussed in other sections of this manual.

Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset is meaningful.

For all Resets, the default clock source is determined by the FNOSC[2:0] bits in the FOSCSEL Configuration register. The value of the FNOSCx bits is loaded into the NOSC[2:0] (OSCCON[10:8]) bits on Reset, which in turn, initializes the system clock.