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15.13.25 IPR3
Peripheral Interrupt Priority Register 3| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | RC2
IP | TX2
IP | RC
1IP | TX
1IP | BCL2
IP | SSP2
IP | BCL
1IP | SSP
1IP | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 5, 7 – RCxIP EUSARTx Receive Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bits 4, 6 – TXxIP EUSARTx Transmit Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bits 1, 3 – BCLxIP MSSPx Bus Collision Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bits 0, 2 – SSPxIP Synchronous Serial Port 'x' Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
