15.13.12 PIE0

Peripheral Interrupt Enable Register 0

Note:

PIR0 interrupts are not disabled by the PEIE bit in the INTCON register.

Name:	PIE0
Offset:	0xE29


Bit	7	6	5	4	3	2	1	0
			TMR0IE	IOCIE	INT3 IE	INT2IE	INT1IE	INT 0IE
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bit 5 – TMR0IE Timer0 Interrupt Enable bit⁽¹⁾

Value	Description
1	Enabled
0	Disabled

Bit 4 – IOCIE Interrupt-on-Change Enable bit⁽¹⁾

Value	Description
1	Enabled
0	Disabled

Bits 0, 1, 2, 3 – INTxIE External Interrupt ‘x’ Enable bit⁽¹⁾

Value	Description
1	Enabled
0	Disabled

PIR0 interrupts are not disabled by the PEIE bit in the INTCON register.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.