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15.13.12 PIE0
Peripheral Interrupt Enable Register 0Note: - PIR0 interrupts are not disabled by the PEIE bit in the INTCON register.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | TMR0IE | IOCIE | INT3
IE | INT2IE | INT1IE | INT
0IE | |
Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 5 – TMR0IE
Timer0 Interrupt Enable bit(1)
Value | Description |
---|
1 |
Enabled |
0 |
Disabled |
Bit 4 – IOCIE
Interrupt-on-Change Enable bit(1)
Value | Description |
---|
1 |
Enabled |
0 |
Disabled |
Bits 0, 1, 2, 3 – INTxIE
External Interrupt ‘x’ Enable bit(1)
Value | Description |
---|
1 |
Enabled |
0 |
Disabled |
PIR0 interrupts are not disabled by the PEIE bit in the INTCON register.