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15.13.15 PIE3
Peripheral Interrupt Enable Register 3| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | RC2
IE | TX2
IE | RC
1IE | TX
1IE | BCL2
IE | SSP2
IE | BCL
1IE | SSP
1IE | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 5, 7 – RCxIE EUSARTx Receive Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bits 4, 6 – TXxIE EUSARTx Transmit Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bits 1, 3 – BCLxIE MSSPx Bus Collision Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bits 0, 2 – SSPxIE Synchronous Serial Port ‘x’ Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
