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15.13.23 IPR1
Peripheral Interrupt Priority Register 1| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | OSCFIP | CSWIP | | | | | ADTIP | ADIP | |
| Access | R/W | R/W | | | | | R/W | R/W | |
| Reset | 1 | 1 | | | | | 1 | 1 | |
Bit 7 – OSCFIP Oscillator Fail Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 6 – CSWIP Clock-Switch Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 1 – ADTIP ADC Threshold Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 0 – ADIP ADC Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
