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15.13.26 IPR4
Peripheral Interrupt Priority Register 4| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | RC5IP | TX5IP | RC4IP | TX4IP | RC3IP | TX3IP | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit 5 – RC5IP EUSART5 Receive Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 4 – TX5IP EUSART5 Transmit Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 3 – RC4IP EUSART4 Receive Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 2 – TX4IP EUSART4 Transmit Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 1 – RC3IP EUSART3 Receive Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 0 – TX3IP EUSART3 Transmit Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
