32.8.9 Status
| Name: | STATUS |
| Offset: | 0x1A |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ITER | TXE | COLL | ISF | CTS | BUFOVF | FERR | PERR | ||
| Access | R/W | R/W | R/W | R/W | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ITER Maximum Number of Repetitions Reached
This bit is set when the maximum number of NACK repetitions or retransmissions is met in the ISO7816 T = 0 mode.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears it.
Bit 6 – TXE Transmitter Empty
When CTRLA.FORM is set to LIN Host mode, this bit is set when any ongoing transmission is complete and TxDATA is empty.
When CTRLA.FORM is not set to LIN Host mode, this bit will always read back as ‘0’.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears it.
Bit 5 – COLL Collision Detected
This bit is cleared by writing ‘1’ to the bit or by disabling the receiver.
This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears it.
Bit 4 – ISF Inconsistent Sync Field
This bit is cleared by writing ‘1’ to the bit or by disabling the receiver.
This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is received.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears it.
Bit 3 – CTS Clear to Send
This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO).
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit has no effect.
Bit 2 – BUFOVF Buffer Overflow
Reading this bit before reading the Data register indicates the error status of the next character to be read.
This bit is cleared by writing ‘1’ to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears it.
Bit 1 – FERR Frame Error
Reading this bit before reading the Data register indicates the error status of the next character to be read.
This bit is cleared by writing ‘1’ to the bit or by disabling the receiver.
This bit is set if the received character had a frame error, in other words, when the first stop bit is ‘0’.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears it.
Bit 0 – PERR Parity Error
Reading this bit before reading the Data register indicates the error status of the next character to be read.
This bit is cleared by writing ‘1’ to the bit or by disabling the receiver.
This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5, or 0x7) and a parity error is detected.
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears it.