32.8.6 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register are also reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
 ERROR RXBRKCTSICRXSRXCTXCDRE 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – ERROR Error Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the Error Interrupt Enable bit, which disables the Error interrupt.

ValueDescription
0Error interrupt is disabled.
1Error interrupt is enabled.

Bit 5 – RXBRK Receive Break Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the Receive Break Interrupt Enable bit, which disables the Receive Break interrupt.

ValueDescription
0Receive Break interrupt is disabled.
1Receive Break interrupt is enabled.

Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To Send Input Change interrupt.

ValueDescription
0Clear To Send Input Change interrupt is disabled.
1Clear To Send Input Change interrupt is enabled.

Bit 3 – RXS Receive Start Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt.

ValueDescription
0Receive Start interrupt is disabled.
1Receive Start interrupt is enabled.

Bit 2 – RXC Receive Complete Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt.

ValueDescription
0Receive Complete interrupt is disabled.
1Receive Complete interrupt is enabled.

Bit 1 – TXC Transmit Complete Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the Transmit Complete Interrupt Enable bit, which disables the Transmit Complete interrupt.

ValueDescription
0Transmit Complete interrupt is disabled.
1Transmit Complete interrupt is enabled.

Bit 0 – DRE Data Register Empty Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt.

ValueDescription
0Data Register Empty interrupt is disabled.
1Data Register Empty interrupt is enabled.