32.8.2 Control B

Name:	CTRLB
Offset:	0x04
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected, Write-Synchronized


Bit	31	30	29	28	27	26	25	24
							LINCMD[1:0]
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
							RXEN	TXEN
Access							R/W	R/W
Reset							0	0


Bit	15	14	13	12	11	10	9	8
			PMODE			ENC	SFDE	COLDEN
Access			R/W			R/W	R/W	R/W
Reset			0			0	0	0


Bit	7	6	5	4	3	2	1	0
		SBMODE				CHSIZE[2:0]
Access		R/W				R/W	R/W	R/W
Reset		0				0	0	0

Bits 25:24 – LINCMD[1:0] LIN Command

These bits define the LIN header transmission control. This field is only valid in LIN Host mode (CTRLA.FORM = LIN Host).

These are strobe bits and always reads back as ‘0’.

These bits are not enable-protected.

Value	Description
0x0	Normal USART transmission.
0x1	Break field is transmitted when DATA is written.
0x2	Break, sync and identifier are automatically transmitted when DATA is written with the identifier.
0x3	Reserved

Bit 17 – RXEN Receiver Enable

Writing ‘0’ to this bit disables the USART receiver. Disabling the receiver flushes the receive buffer and clears the FERR, PERR and BUFOVF bits in the STATUS register.

Writing ‘1’ to CTRLB.RXEN when the USART is disabled sets CTRLB.RXEN immediately. When the USART is enabled, CTRLB.RXEN is cleared and SYNCBUSY.CTRLB is set and remains set until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN reads back as ‘1’.

Writing ‘1’ to CTRLB.RXEN when the USART is enabled sets SYNCBUSY.CTRLB, which remains set until the receiver is enabled and CTRLB.RXEN reads back as ‘1’.

This bit is not enable-protected.

Value	Description
0	The receiver is disabled or being enabled.
1	The receiver is enabled or is enabled when the USART is enabled.

Bit 16 – TXEN Transmitter Enable

Writing ‘0’ to this bit disables the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed.

Writing ‘1’ to CTRLB.TXEN when the USART is disabled sets CTRLB.TXEN immediately. When the USART is enabled, CTRLB.TXEN is cleared and SYNCBUSY.CTRLB is set and remains set until the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN reads back as ‘1’.

Writing ‘1’ to CTRLB.TXEN when the USART is enabled sets SYNCBUSY.CTRLB, which remains set until the transmitter is enabled and CTRLB.TXEN reads back as ‘1’.

This bit is not enable-protected.

Value	Description
0	The transmitter is disabled or being enabled.
1	The transmitter is enabled or is enabled when the USART is enabled.

Bit 13 – PMODE Parity Mode

This bit selects the type of parity used when parity is enabled (CTRLA.FORM is ‘1’). The transmitter automatically generates and sends the parity of the transmitted data bits within each frame. The receiver generates a parity value for the incoming data and parity bit, compares it to the Parity mode and, if a mismatch is detected, sets STATUS.PERR.

This bit is not synchronized.

Value	Description
0	Even parity
1	Odd parity

Bit 10 – ENC Encoding Format

This bit selects the data encoding format.

This bit is not synchronized.

Value	Description
0	Data is not encoded.
1	Data is IrDA encoded.

Bit 9 – SFDE Start of Frame Detection Enable

This bit controls whether the start-of-frame detector wakes up the device when a start bit is detected on the RxD line.

This bit is not synchronized.


SFDE	INTENSET.RXS	INTENSET.RXC	Description
0	X	X	Start-of-frame detection disabled
1	0	0	Reserved
1	0	1	Start-of-frame detection enabled. RXC wakes up the device from all Sleep modes.
1	1	0	Start-of-frame detection enabled. RXS wakes up the device from all Sleep modes.
1	1	1	Start-of-frame detection enabled. Both RXC and RXS wake up the device from all Sleep modes.