32.8.3 Control C

Name: CTRLC
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
       DATA32B[1:0] 
Access R/WR/W 
Reset 00 
Bit 2322212019181716 
  MAXITER[2:0]  DSNACKINACK 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 15141312111098 
     HDRDLY[1:0]BRKLEN[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
      GTIME[2:0] 
Access R/WR/WR/W 
Reset 000 

Bits 25:24 – DATA32B[1:0] Data 32-Bit

These bits configure the 32-bit extension for read and write transactions to the DATA register.

When disabled, access is according to CTRLB.CHSIZE.

ValueDescription
0x0

DATA reads (for received data) and writes (for transmit data) according to CTRLB.CHSIZE.

0x1

DATA reads according to CTRLB.CHSIZE.

DATA writes using 32-bit extension.

0x2

DATA reads using 32-bit extension.

DATA writes according to CTRLB.CHSIZE.

0x3

DATA reads and writes using 32-bit extension.

Bits 22:20 – MAXITER[2:0] Maximum Iterations

These bits define the maximum number of retransmit iterations.

These bits also define the successive NACKs sent to the remote transmitter when CTRLC.DSNACK is set.

This field is only valid when using ISO7816 T = 0 mode (CTRLA.MODE = 0x7 and CTRLA.CMODE = 0).

Bit 17 – DSNACK Disable Successive Not Acknowledge

This bit controls how many times NACK is sent on parity error reception.

This bit is only valid in ISO7816 T = 0 mode and when CTRLC.INACK = 0.

ValueDescription
0NACK is sent on the ISO line for every parity error received.
1Successive parity errors are counted up to the value specified in CTRLC.MAXITER. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line.

Bit 16 – INACK Inhibit Not Acknowledge

This bit controls whether a NACK is transmitted when a parity error is received.

This bit is only valid in ISO7816 T = 0 mode.

ValueDescription
0NACK is transmitted when a parity error is received.
1NACK is not transmitted when a parity error is received.

Bits 11:10 – HDRDLY[1:0] LIN Host Header Delay

These bits define the delay between break and sync transmission, in addition to the delay between the sync and identifier (ID) fields when in LIN Host mode (CTRLA.FORM = 0x2).

This field is only valid when using the LIN header command (CTRLB.LINCMD = 0x2).

ValueDescription
0x0

Delay between break and sync transmission is 1-bit time.

Delay between sync and ID transmission is 1-bit time.

0x1

Delay between break and sync transmission is 4-bit time.

Delay between sync and ID transmission is 4-bit time.

0x2

Delay between break and sync transmission is 8-bit time.

Delay between sync and ID transmission is 8-bit time.

0x3

Delay between break and sync transmission is 14-bit time.

Delay between sync and ID transmission is 14-bit time.

Bits 9:8 – BRKLEN[1:0] LIN Host Break Length

These bits define the length of the break field transmitted when in LIN Host mode (CTRLA.FORM = 0x2).
ValueDescription
0x0Break field transmission is 13-bit times
0x1Break field transmission is 17-bit times
0x2Break field transmission is 21-bit times
0x3Break field transmission is 26-bit times

Bits 2:0 – GTIME[2:0] Guard Time

These bits define the guard time when using RS485 mode (CTRLA.FORM = 0x0 or CTRLA.FORM = 0x1 and CTRLA.TXPO = 0x3) or ISO7816 mode (CTRLA.FORM = 0x7).

For RS485 mode, the guard time is programmable from 0-7-bit times and defines the time that the transmit enable pin (TE) remains high after the last stop bit is transmitted and there is no remaining data to be transmitted.

For ISO7816 T = 0 mode, the guard time is programmable from 2-9-bit times and defines the guard time between each transmitted byte.