1.6.7 Transceivers

PolarFire devices include up to 24 transceiver lanes organized in four lane quads. Each device also contains two PCIe controllers within a select quad as ASIC IP blocks. The transceiver complex consists of many sub-blocks that are interconnected via flash cell controlled interconnects and register set updates to realize a user configured design. The complexities of interconnecting these blocks and setting register values are handled automatically by the Libero SoC design tool. Unused Transceiver lanes, supporting logic blocks and PCIe IP have their register set configured into a low power, reset configuration by the Libero SoC tool. Furthermore, the Libero SoC design tool ties all fabric sourced input pins to these IP blocks to a disabled logic level through SEU immune fabric flash bits.

There are SEU immune and flash-based lock bits for each transceiver register. However, due to the interdependencies of the transceiver building blocks, it is recommended to leave the lock bits set to the unlocked state for all transceiver building block registers that are modified. This includes all quad building blocks that are named "Qx_*" and the PCIe building blocks named "PCIEx_*". Doing this ensures that the blocks get correctly configured. For more information about registers and lock bits, see Device Configuration Report and Register Locks section.

The status of these blocks can be monitored by reading the appropriate status registers using the dynamic reconfiguration interface (DRI). Only instantiation of the DRI IP is required. See PolarFire Device Register Map for address map of Transceiver/PCIe control and status registers. For information about how to use DRI for dynamic register configuration, see AN4592: PolarFire FPGA Dynamic Reconfiguration Interface Application Note .