1.6.3 CCC

Clock conditioning circuits provide PLL/DLL sourced clocking to the device. The Libero SoC tool automatically configures these IP blocks based on the designer's configuration, removing complexities from the designer. When a CCC is not in use, the Libero SoC tool leaves the CCC in its default configuration and tie all FPGA fabric sourced inputs to a disabled logic-level through fabric flash bits. The CCC has a block-level SEU immune, flash-based, register lock bit that can be enabled when the IP is unused or if the IP is used but no dynamic configuration changes are part of the user design. This provides further assurance that the block configuration remains unchanged. For more information about registers and lock bits, see Device Configuration Report and Register Locks section.

The status of the CCCs can be monitored by reading the appropriate CCC status registers using the dynamic reconfiguration interface (DRI). For information about how to use DRI for dynamic register configuration, see AN4592: PolarFire FPGA Dynamic Reconfiguration Interface Application Note .

Important: Note that the hard IP blocks do not require to be instantiated in the design to read the status registers using DRI. See PolarFire Device Register Map for address map of CCC control and status registers.