1.6.1 Device I/O

All GPIO and HSIO are configured with SEU immune flash bits. Unused user GPIO and HSIO are tristated with internal weak pull-up resistors. These I/O banks have built-in calibration circuits required for features such as ODT, drive, and slew control. The calibration process runs automatically at device power-up and results in calibration codes stored in volatile registers that are subject to SEU. I/O bank's suspected to be affected by an SEU can be manually re-calibrated using the PF_INIT_MONITOR IP module. For more information, see PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide .