1.6.2 Advanced I/O capabilities

I/O banks contain many advanced features including DDR with configurable clock alignments, clock and data recovery (CDR) and various memory interfaces. There are ASIC IP building blocks in the PolarFire family of devices to support these advanced capabilities. The Libero® SoC tool automatically configures these building blocks based on the designer's configuration in the tool, removing complexities from the designer. When these advanced features are not in use, the Libero SoC tool leaves these blocks in their default configurations and tie all FPGA fabric sourced inputs to a disabled logic-level through fabric flash bits. These building blocks have block-level SEU immune, flash-based, register lock bits that can be enabled to avoid inadvertent changes to the configuration registers. This provides further assurance that the block configuration remains unchanged. For more information about registers and lock bits, see Device Configuration Report and Register Locks section.