1.2.10 reset_delay
(Ask a Question)reset_delay is a user-defined RTL module, which delays the TX reset signals I_SYS_TX_SRESET and I_PCS49_TX_SRESET of CORE10GMAC by 32 clock cycles to assert the reset once the TX clocks are stable.
reset_delay is a user-defined RTL module, which delays the TX reset signals I_SYS_TX_SRESET and I_PCS49_TX_SRESET of CORE10GMAC by 32 clock cycles to assert the reset once the TX clocks are stable.
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