47.5.12.5 Audio Protocol Modes
The Audio function supports several protocol modes of operation using the AUDMOD, FRMCNT, FRMSYPW and AUDFMT registers. I2STPD - Hosts with clients Transmit Packed data mode is supported using the TPD_EN, DATFMT_LR, MST_SLV_EN[4:0], SLV_M-ST_UPPR, FRMCNT, and FRMSYPW registers. TDM mode is supported using the FRMCNT, TDMSSZ, TDMWSZ, TDM_EN, DATFILL, FRMCNT, and FRMSYPW. The macro uses these modes to communicate with different types of codecs. These modes control the edge relationships of LRC and SDI/SDO with respect to SCK.
For most combinations of audio data length, channel length and frame length, there are at least as many or more serial clocks than data to transmit. When this macro is the transmitter it pads all extra clocks with zeros.
All protocol modes transmit MSB first, followed by MSB-1, and so on, until the LSB transmits. Unlike the I2S (I8S) standard all Audio Protocol functions (including I2S. I8S) implemented by SPI require at least as many or more serial clocks as data to transmit or receive the audio data correctly.
Clock requirements for SCK and LRC differ between host and client setting. The client setting is less stringent. When a host, the Audio Protocol function only supports frame sizes of 32, 64, or 256 clocks. However, when a client and I2S legacy mode AUDFMT=000, the Audio Protocol function only requires at least the number of clocks selected by MODE[32,16] or AUDWD_MODE[1,0], other wise in client mode and with new Audio Protocol functions selected AUDFMT ~= 000, the number of clocks required is 32 clocks per channel word.
I8S is allowing multiple channels of data to be transmitted on a single data line. The I8S interface is similar to the 2 channel serial audio interface I2S with the exception that more channels are transmitted within a sample frame or sample period, basically defined as an 8 channel TDM interface (left or right justified) with a 50% duty cycle LRC clock. As with the I2S interface the I8S interface is comprised of two control clocks, a frame synchronization pulse (LRC), a serial clock (SCK) and the serial audio data line (SDO/SDI). Several Audio Modes can be selected, i.e., I2S, I8S, right justified, left justified, packed 24x4bit raw, packed 2x16 raw, Host with clients transmit Packed data and TDM.
I2S (AUDMOD=00, AUDFMT=000)
In I2S mode, the transmitter drives the MSB of the audio data on the first falling edge of SCK after an LRC transition. The receiver samples the MSB on the second rising edge of SCK. The left channel data transmits while LRC is low and the right channel transmits while LRC is high. A frame transmits left channel first then right channel.
To be I2S compliant, the configuration bits in SPIxC- TRL_* must be set as follows: AUDEN=1, AUD- MOD=00, FRMPOL=0, CPOL=1, CPHA = 1, FRMSYPW=0001, FRMCNT=001, AUDFMT[2:0] =000, FRMCOINC=0. These values set SDO and LRC transitions to occur on the falling edge of SCK and sampling of SDI to occur on the rising edge of SCK. It also starts a frame with LRC falling edge transition.
Left Justified (AUDMOD=01 AUDFMT=000)
In Left Justified mode, the transmitter drives the audio data’s MSB on the SCK edge that is coincident with an LRC transition. The receiver samples the MSB on the next SCK edge.
Codecs using justified protocols usually default to transmitting data on the rising edge of SCK and receiving data on the falling edge of SCK. Another convention is that LRC is high for the left channel and low for the right channel which is opposite of I2S. But they maintain left channel followed by right channel (in a frame).
Many codecs support other options but to configure for the left justified standard convention set the following bits in SPIxCTRL_* as follows: AUDEN=1, AUD- MOD=01, FRMPOL=1, CPOL=0, CPHA = 1, FRM- SYPW=0001, FRMCNT=001, AUDFMT[2:0] = 000, FRMEN=1. FRMCOINC=1. The following figures show waveforms for this configuration.
Format for 20 bit Audio Data and 32-bit channel, transmitted or received as if it were a 24bit data word made up of the 20 bit sample data MSB left justified in the 24 bit word and remaining 4 bits are zeros, then left justified mode as a 24 bit word.
Right Justified (AUDMOD=10 AUDFMT=000)
In Right Justified mode, the transmitter drives the audio data’s MSB on the nth transmit edge of SCK such that the LSB is available on the receive edge of SCK preceding a transition of LRC.
When set to transmit (DISSDO = 0), this device drives the unused bit slots (preceding the audio data) with logic level 0. When set to receive (DISSDI = 0), this device ignores the unused bit slot.
The following figures show right justified mode configured as follows: AUDEN=1, AUDMOD=10, FRMPOL=1, CPOL=0, CPHA = 1, FRMSYPW=0001, FRMCNT=001, AUDFMT[2:0] = 000, FRMCOINC=1.
Format for 20 bit Audio Data and 32-bit channel, transmitted or received as if it was a 24bit data word made up of the 20 bit sample data MSB left justified in the 24 bit word and remaining 4 bits are zeros, then right justified mode as a 24 bit word.
PCM/DSP (AUDMOD=11 AUDFMT=000)
The PCM/DSP protocol mode is available for communication with some codecs and certain DSP devices. This mode modifies the behavior of LRC and audio data spacing.
In PCM/DSP mode the LRC can be single bit wide (i.e., 1 SCK) or as wide as the audio data (16,20,24,32-bits). The audio data is packed in the frame with the left channel data immediately followed by the right channel data. The frame length is still either 32 or 64 clocks when this device is the host.
In PCM/DSP mode, the transmitter drives the audio data’s (left channel) MSB on the first or second transmit edge (See SPIxCTRL_*.FRMCOINC) of SCK (after an LRC transition). Immediately after the (left channel) LSB, the transmitter drives the (right channel) MSB.
