47.5.12.8 Host Mode Clocking
The SPI uses GCLK to generate SCK and LRC.
The use of an on chip ClockOut source. This clock source can also be driven out a pin to be used as MCLK by the CODEC.
Typically the ClockOut feature supports the System Clock and, if available, the USB Clock as a source. The ClockOut peripheral divides the source clock to a frequency that can be driven out of the chip.
SCK and LRC Clock Generation
MODE[32,16] or AUDWD_MODE[1:0] defines the relationship between LRC and SCK. When a frame is 64-bits SCK is 64x the frequency of LRC. When a frame is 32-bits SCK is 32x the frequency of LRC.
Since LRC toggles at the sample rate (Fs), SCK’s frequency must be derived from it. To setup SPIxBRG, divide the desired sample rate by the GCLK or MCLK frequency (whichever is being used). Then, divide the resulting number by the frame size (either 32 or 64). Program this value into SPIxBRG. If a whole number is not the result, error will be present in your actual sample rate.
MCLK Support
The use of a RefOut (reference clock output) peripheral to generate MCLK for the CODEC is not a perfect choice. Driving a clock out an I/O Pad induces jitter that may degrade audio fidelity of the CODEC. The best solution is for the CODEC to use a crystal and be the host I2S/Audio device.
In lieu of the CODEC generating MCLK (including SCK and LRC), the next best choice is for the RefOut peripheral to generate MCLK with the CODEC being the Host I2S. In this configuration the CODEC can use any of its timing dividers to achieve the necessary clocking results for SCK and LRC.
Also, RefOut peripherals generally support 12MHz and 24MHz derived from a USB PLL. Typical audio MCLK frequencies of 12.288MHz and 11.2896MHz cannot be obtained using USB clock frequencies.
